/*
 * Copyright (c) 2022, IMMORTA Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without modification,
 * are permitted provided that the following conditions are met:
 *
 * - Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
 *
 * - Redistributions in binary form must reproduce the above copyright notice, this
 *   list of conditions and the following disclaimer in the documentation and/or
 *   other materials provided with the distribution.
 *
 * - Neither the name of IMMORTA Inc. nor the names of its
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef IM94_CONFIG_H
#define IM94_CONFIG_H

/*!
 * @file IM94_config.h
 * @brief This file provide chip specific module features config
 */

/*******Includes***************************************************************/

/*******Definitions************************************************************/

/********************* UART module config *************************************/
/*! @brief Array initializer of UART peripheral register base pointers */
#define CONFIG_UART_REG_BASE_PTRS           { UART0, UART1, UART2, UART3 }

#define CONFIG_UART_CLOCK_NAMES             { CLK_UART0, CLK_UART1, CLK_UART2, CLK_UART3 }
#define CONFIG_UART_MODULE_NAMES            { MODULE_UART0, MODULE_UART1, MODULE_UART2, MODULE_UART3 }
#define CONFIG_UART_TX_DMA_REQS             { DMA_REQ_UART0_TX, DMA_REQ_UART1_TX, DMA_REQ_UART2_TX, DMA_REQ_UART3_TX }
#define CONFIG_UART_RX_DMA_REQS             { DMA_REQ_UART0_RX, DMA_REQ_UART1_RX, DMA_REQ_UART2_RX, DMA_REQ_UART3_RX }
#define CONFIG_UART_TX_FIFO_DEPTH           (2U)

/*! @brief Interrupt vectors for the UART peripheral type */
#define CONFIG_UART_IRQS                    { UART0_IRQn,  UART1_IRQn, UART2_IRQn, UART3_IRQn }
#define CONFIG_UART_INSTANCE_COUNT          (4U)

/********************* ADC module config **************************************/
/*! @brief Array initializer of ADC peripheral register base pointers */
#define CONFIG_ADC_REG_BASE_PTRS            { ADC0, ADC1}
/*! @brief Array initializer of ADC peripheral base addresses */
#define CONFIG_ADC_BASE_ADDRS               { ADC0_BASE, ADC1_BASE }
/*! @brief Array initializer of ADC clk name */
#define CONFIG_ADC_CLOCK_NAMES              { CLK_ADC0, CLK_ADC1}
/*! @brief Array initializer of ADC module name */
#define CONFIG_ADC_MODULE_NAMES             { MODULE_ADC0, MODULE_ADC1 }
/*! @brief Interrupt vectors for the ADC peripheral type */
#define CONFIG_ADC_IRQS                     { ADC0_IRQn, ADC1_IRQn }
/*! @brief ADC instance counts */
#define CONFIG_ADC_INSTANCE_COUNT           (2U)
/*! @brief ADC dma request */
#define CONFIG_ADC_DMA_REQS                 { DMA_REQ_ADC0, DMA_REQ_ADC1 }
/*! @brief ADC max normal sequence length */
#define CONFIG_ADC_MAX_NORMAL_SEQUENCE_LEN   (20U)
/*! @brief ADC max priority sequence length */
#define CONFIG_ADC_MAX_PRIORITY_SEQUENCE_LEN (4U)
/*! @brief ADC support vrefl */
#define CONFIG_ADC_SUPPORT_VREFL             (1U)

/********************* GPIO module config **************************************/
/*! @brief Array initializer of GPIO peripheral register base pointers */
#define CONFIG_GPIO_REG_BASE_PTRS           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE}
/*! @brief Array initializer of GPIO peripheral base addresses */
#define CONFIG_GPIO_BASE_ADDRS              { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
/*! @brief Interrupt vectors for the GPIO peripheral type */
#define CONFIG_GPIO_IRQS                    { GPIOA_IRQn,  GPIOB_IRQn, GPIOC_IRQn, GPIOD_IRQn, GPIOE_IRQn }
/*! @brief GPIO PORT counts */
#define CONFIG_GPIO_PORT_COUNT              (5U)
/*! @brief GPIO PORT pin counts */
#define CONFIG_GPIO_PIN_COUNT               (18U)
/*! @brief GPIO support independent digital filter length */
#define CONFIG_GPIO_SUPPORT_INDEPENDENT_DFL (1U)

/********************* CRC module config **************************************/
/*! @brief Array initializer of CRC peripheral register base pointers */
#define CONFIG_CRC_REG_BASE_PTRS            { CRC }
/*! @brief Array initializer of CRC peripheral base addresses */
#define CONFIG_CRC_BASE_ADDRS               { CRC_BASE }
/*! @brief Array initializer of CRC module name */
#define CONFIG_CRC_MODULE_NAMES             { MODULE_CRC }
/*! @brief CRC instance counts */
#define CONFIG_CRC_INSTANCE_COUNT           (1U)

/********************* I2C module config **************************************/
/*! @brief Array initializer of I2C peripheral register base pointers */
#define CONFIG_I2C_REG_BASE_PTRS            { I2C0, I2C1 }
/*! @brief Array initializer of I2C clock name */
#define CONFIG_I2C_CLOCK_NAMES              { CLK_I2C0, CLK_I2C1 }
/*! @brief Array initializer of I2C module name */
#define CONFIG_I2C_MODULE_NAMES             { MODULE_I2C0, MODULE_I2C1 }
/*! @brief Array initializer of I2C interrupt request number */
#define CONFIG_I2C_IRQS                     { I2C0_IRQn, I2C1_IRQn }
/*! @brief Array initializer of I2C RX dma request number */
#define CONFIG_I2C_RX_DMA_REQS              { DMA_REQ_I2C0_RX, DMA_REQ_I2C1_RX }
/*! @brief Array initializer of I2C TX dma request number */
#define CONFIG_I2C_TX_DMA_REQS              { DMA_REQ_I2C0_TX, DMA_REQ_I2C1_TX }
/*! @brief Array initializer of I2C instance counts */
#define CONFIG_I2C_INSTANCE_COUNT           (2U)

/********************* ERM module config **************************************/
/*! @brief Array initializer of ERM peripheral register base pointers */
#define CONFIG_ERM_REG_BASE_PTRS            { ERM }
/*! @brief ERM instance counts */
#define CONFIG_ERM_INSTANCE_COUNT               (1U)
/*! @brief ERM clock is always on*/
#define CONFIG_ERM_ALWAYS_CLOCK_ON              (1U)
/*! @brief ERM pflash and dflash are controlled separately*/
#define CONFIG_ERM_FLASH_SEPARATED_ECC_CONTROL  (1U)

/********************* FLASH module config **************************************/
/*! @brief Array initializer of FLASH peripheral register base pointers */
#define CONFIG_FLASH_REG_BASE_PTRS          { FLASH }
/*! @brief Array initializer of FLASH peripheral base addresses */
#define CONFIG_FLASH_BASE_ADDRS             { FLASH_BASE }
/*! @brief Read protection feature */
#define CONFIG_FLASH_READ_PROTECT_FEATURE   (0U)
/*! @brief Flash debug protection feature */
#define CONFIG_FLASH_DEBUG_PROTECT_FEATURE  (1U)
/*! @brief Flash unlock two sequences */
#define CONFIG_FLASH_UNLOCK_TWO_SEQUENCES   (0U)
/*! @brief Number of cache */
#define CONFIG_FLASH_NUMBER_OF_CACHE        (2U)
/*! @brief Is chip multiple master:host core & hsm core */
#define CONFIG_FLASH_CHIP_MULTI_MASTER      (1U)
/*! @brief PFlash size */
#define CONFIG_FLASH_PFLASH_SIZE            (0x100000U)
/*! @brief DFlash size */
#define CONFIG_FLASH_DFLASH_SIZE            (0x20000U)
/*! @brief Number of pflash block */
#define CONFIG_PFLASH_NUMBER_OF_BLOCK       (2U)
/*! @brief Number of pflash page */
#define CONFIG_PFLASH_NUMBER_OF_PAGE        (512U)
/*! @brief Number of dflash page */
#define CONFIG_DFLASH_NUMBER_OF_PAGE        (64U)
/*! @brief Number of option byte fields */
#define CONFIG_FLASH_NUMBER_OF_OPB_FIELD    (3U)
/*! @brief Option byte:debug protection & write protection */
#define CONFIG_FLASH_RP_WP_OPB_SIZE         (0xA8)
/*! @brief Option byte:debug authorization key */
#define CONFIG_FLASH_DGB_KEY_OPB_SIZE       (0x40)
/*! @brief Option byte: A/B SWAP */
#define CONFIG_FLASH_AB_SWAP_OPB_SIZE       (0x10)
/*! @brief Flash OTA feature */
#define CONFIG_FLASH_AB_SWAP_FEATURE        (1U)

/********************* DMA module config **************************************/
/*!
 * @brief DMA request source
 */
typedef enum {
    DMA_REQ_ADC0 = 0x00U,
    DMA_REQ_UART0_TX,
    DMA_REQ_UART0_RX,
    DMA_REQ_UART1_TX,
    DMA_REQ_UART1_RX,
    DMA_REQ_UART2_TX,
    DMA_REQ_UART2_RX,
    DMA_REQ_UART3_TX,
    DMA_REQ_UART3_RX,
    DMA_REQ_I2C0_TX,
    DMA_REQ_I2C0_RX,
    DMA_REQ_I2C1_TX,
    DMA_REQ_I2C1_RX,
    DMA_REQ_SPI0_TX,
    DMA_REQ_SPI0_RX,
    DMA_REQ_SPI1_TX,
    DMA_REQ_SPI1_RX,
    DMA_REQ_SPI2_TX,
    DMA_REQ_SPI2_RX,
    DMA_REQ_SPI3_TX,
    DMA_REQ_SPI3_RX,
    DMA_REQ_ADC1,
    DMA_REQ_DISABLE = 0xFFU,
} dma_perial_request_t;

#define CONFIG_DMA_CH_BASE_ADDRS            { DMA_CH0, DMA_CH1, DMA_CH2, DMA_CH3, DMA_CH4, DMA_CH5, DMA_CH6, DMA_CH7 }
#define CONFIG_DMA_IRQS                     { DMA_Channel0_IRQn, DMA_Channel1_IRQn, DMA_Channel2_IRQn, DMA_Channel3_IRQn, \
                                              DMA_Channel4_IRQn, DMA_Channel5_IRQn, DMA_Channel6_IRQn, DMA_Channel7_IRQn }
#define CONFIG_DMA_CH_COUNT                 (8U)

/********************* CLOCK module config ************************************/
/*!
 * @brief Clock names
 */
typedef enum {
    /* System clock sources, 0x00U ~ 0x0FU */
    CLK_HSI             = 0x00U, /*!< High Speed Internal RC */
    CLK_LSI             = 0x01U, /*!< Low Speed Internal RC */
    CLK_HSE             = 0x02U, /*!< High Speed External clock */
    CLK_LSE             = 0x03U, /*!< Low Speed External clock(RTC_CLKIN) */
    CLK_PLL             = 0x04U, /*!< PLL, 120MHz */
    CLK_END_OF_SRC      = 0x0FU, /*!< End of system clock sources */

    /* Main clocks used by modules, 0x10U ~ 0x1FU */
    CLK_SYS             = 0x10U, /*!< System clock */
    CLK_AHB             = 0x11U, /*!< AHB clock */
    CLK_APB             = 0x12U, /*!< APB clock */
    CLK_PERI0           = 0x13U, /*!< Peripheral0 clock */
    CLK_PERI1           = 0x14U, /*!< Peripheral1 clock */
    CLK_END_OF_INTERNAL = 0x1FU, /*!< End of main clocks */

    /* Module functional clocks, 0x20U ~ 0xFFU */
    CLK_I2C0            = 0x20U, /*!< Clock for I2C0 */
    CLK_I2C1            = 0x21U, /*!< Clock for I2C1 */
    CLK_UART0           = 0x22U, /*!< Clock for UART0 */
    CLK_UART1           = 0x23U, /*!< Clock for UART1 */
    CLK_UART2           = 0x24U, /*!< Clock for UART2 */
    CLK_UART3           = 0x25U, /*!< Clock for UART3 */
    CLK_CAN0            = 0x26U, /*!< Clock for CAN0 */
    CLK_CAN1            = 0x27U, /*!< Clock for CAN1 */
    CLK_CAN2            = 0x28U, /*!< Clock for CAN2 */
    CLK_SPI0            = 0x29U, /*!< Clock for SPI0 */
    CLK_SPI1            = 0x2AU, /*!< Clock for SPI1 */
    CLK_SPI2            = 0x2BU, /*!< Clock for SPI2 */
    CLK_SPI3            = 0x2CU, /*!< Clock for SPI3 */
    CLK_TIMER0          = 0x2DU, /*!< Clock for TIMER0 */
    CLK_TIMER1          = 0x2EU, /*!< Clock for TIMER1 */
    CLK_TIMER2          = 0x2FU, /*!< Clock for TIMER2 */
    CLK_TIMER3          = 0x30U, /*!< Clock for TIMER3 */
    CLK_CMP0            = 0x31U, /*!< Clock for CMP0 */
    CLK_ADC0            = 0x32U, /*!< Clock for ADC0 */
    CLK_ADC1            = 0x33U, /*!< Clock for ADC1 */
    CLK_ICM             = 0x34U, /*!< Clock for ICM */
    CLK_DMA             = 0x35U, /*!< Clock for DMA */
    CLK_GPIO            = 0x36U, /*!< Clock for GPIO */
    CLK_CRC             = 0x37U, /*!< Clock for CRC */
    CLK_HSM             = 0x38U, /*!< Clock for HSM */
    CLK_SPWM0           = 0x39U, /*!< Clock for SPWM0 */
    CLK_SPWM1           = 0x3AU, /*!< Clock for SPWM1 */
    CLK_SPWM2           = 0x3BU, /*!< Clock for SPWM2 */
    CLK_IPWM0           = 0x3CU, /*!< Clock for IPWM0 */
    CLK_IPWM1           = 0x3DU, /*!< Clock for IPWM1 */
    CLK_ERM             = 0x3EU, /*!< Clock for ERM */
    CLK_FLASH           = 0x3FU, /*!< Clock for Flash */
    CLK_END_OF_MODULE   = 0xFFU  /*!< End of module clocks */
} clk_names_t;

/*!
 * @brief Module names, for module bus clocks and soft reset
 */
typedef enum {
    /* APB modules */
    MODULE_I2C0         = 0x00U, /*!< I2C0 */
    MODULE_I2C1         = 0x01U, /*!< I2C1 */
    MODULE_UART0        = 0x02U, /*!< UART0 */
    MODULE_UART1        = 0x03U, /*!< UART1 */
    MODULE_UART2        = 0x04U, /*!< UART2 */
    MODULE_UART3        = 0x05U, /*!< UART3 */
    MODULE_SPI0         = 0x07U, /*!< SPI0 */
    MODULE_SPI1         = 0x08U, /*!< SPI1 */
    MODULE_SPI2         = 0x09U, /*!< SPI2 */
    MODULE_SPI3         = 0x0AU, /*!< SPI3 */
    MODULE_CAN0         = 0x0BU, /*!< CAN0 */
    MODULE_CAN1         = 0x0CU, /*!< CAN1 */
    MODULE_CAN2         = 0x0DU, /*!< CAN2 */
    MODULE_TIMER0       = 0x0EU, /*!< TIMER0 */
    MODULE_TIMER1       = 0x0FU, /*!< TIMER1 */
    MODULE_TIMER2       = 0x10U, /*!< TIMER2 */
    MODULE_TIMER3       = 0x11U, /*!< TIMER3 */
    MODULE_CMP0         = 0x12U, /*!< CMP0 */
    MODULE_ADC0         = 0x13U, /*!< ADC0 */
    MODULE_ADC1         = 0x14U, /*!< ADC1 */
    MODULE_ICM          = 0x15U, /*!< ICM */

    /* AHB modules */
    MODULE_DMA          = 0x20U, /*!< DMA */
    MODULE_CRC          = 0x22U, /*!< CRC */
    MODULE_SPWM0        = 0x24U, /*!< SPWM0 */
    MODULE_SPWM1        = 0x25U, /*!< SPWM1 */
    MODULE_SPWM2        = 0x26U, /*!< SPWM2 */
    MODULE_IPWM0        = 0x28U, /*!< IPWM0 */
    MODULE_IPWM1        = 0x29U, /*!< IPWM1 */
    MODULE_MAX          = 0x2AU  /*!< Maximum value */
} module_names_t;

/*! @brief New features included in IM94XX */
#define CONFIG_CLOCK_NEW_FEATURES           (1U)

/********************* RESET module config ************************************/
/*! @brief HSMERR reset feature */
#define CONFIG_RESET_HSMERR_FEATURE         (1U)

/********************* RTC module config **************************************/
/*! @brief Array initializer of RTC peripheral register base pointers */
#define CONFIG_RTC_REG_BASE_PTRS            { RTC }
/*! @brief Array initializer of RTC interrupt request number */
#define CONFIG_RTC_IRQS                     { RTC_IRQn }
/*! @brief Array initializer of RTC instance counts */
#define CONFIG_RTC_INSTANCE_COUNT           (1U)

/********************* CAN module config **************************************/
/*! @brief Array initializer of CAN peripheral register base pointers */
#define CONFIG_CAN_REG_BASE_PTRS            { CAN0, CAN1 , CAN2 }
/*! @brief Array initializer of CAN interrupt request number */
#define CONFIG_CAN_IRQS                     { CAN0_IRQn, CAN1_IRQn, CAN2_IRQn }
/*! @brief Modules for CAN peripheral */
#define CONFIG_CAN_MODULE_NAMES             { MODULE_CAN0 , MODULE_CAN1, MODULE_CAN2}
/*! @brief function clock for CAN peripheral */
#define CONFIG_CAN_CLK_NAMES                { CLK_CAN0, CLK_CAN1, CLK_CAN2 }
/*! @brief CAN instance counts */
#define CONFIG_CAN_INSTANCE_COUNT           (3U)
/*! @brief CAN message buffer, PTB,STB and RX FIFO */
#define CONFIG_CAN_MAX_MB_NUM               (3U)
/*! @brief CAN rx fifo filter nums */
#define CONFIG_CAN_MAX_FILTER_NUM           (22U)
/*! @brief CAN irq handler position */
#define CONFIG_CAN_IRQ_HANDLER_POS          (0U)

/********************* TIMER module config ************************************/
/*! @brief Array initializer of TIMER peripheral register base pointers */
#define CONFIG_TIMER_REG_BASE_PTRS          { TIMER0, TIMER1, TIMER2, TIMER3 }
/*! @brief Array initializer of TIMER clock names */
#define CONFIG_TIMER_CLOCK_NAMES            { CLK_TIMER0, CLK_TIMER1, CLK_TIMER2, CLK_TIMER3 }
/*! @brief Array initializer of TIMER module names */
#define CONFIG_TIMER_MODULE_NAMES           { MODULE_TIMER0, MODULE_TIMER1, MODULE_TIMER2, MODULE_TIMER3 }
/*! @brief Array initializer of TIMER source clock */
#define CONFIG_TIMER_DEFAULT_SRCCLK         { TIMER_CLK_SRC_OFF, TIMER_CLK_SRC_OFF, TIMER_CLK_SRC_OFF, TIMER_CLK_SRC_OFF }
/*! @brief Array initializer of TIMER interrupt vector numbers */
#define CONFIG_TIMER_IRQS                   { TIMER0_IRQn, TIMER1_IRQn, TIMER2_IRQn, TIMER3_IRQn }
/*! @brief Array initializer of TIMER instance counts */
#define CONFIG_TIMER_INSTANCE_COUNT         (4U)

/********************* IPWM module config *************************************/
/*! @brief Array initializer of IPWM peripheral register base pointers */
#define CONFIG_IPWM_REG_BASE_PTRS           { IPWM0, IPWM1 }
/*! @brief Array initializer of IPWM peripheral register base addresses */
#define CONFIG_IPWM_BASE_ADDRS              { IPWM0_BASE, IPWM1_BASE }
/*! @brief Array initializer of IPWM clk name */
#define CONFIG_IPWM_CLOCK_NAMES             { CLK_IPWM0, CLK_IPWM1 }
/*! @brief Array initializer of IPWM module name */
#define CONFIG_IPWM_MODULE_NAMES            { MODULE_IPWM0, MODULE_IPWM1 }
/*! @brief Channel Interrupt vectors for the IPWM peripheral type */
#define CONFIG_IPWM_CHANNEL_IRQS            { IPWM0_Channel_IRQn, IPWM1_Channel_IRQn }
/*! @brief Overflow Interrupt vectors for the IPWM peripheral type */
#define CONFIG_IPWM_OVERFLOW_IRQS           { IPWM0_Overflow_IRQn, IPWM1_Overflow_IRQn }
/*! @brief IPWM unified interrupt */
#define CONFIG_IPWM_UNIFIED_IRQ_FEATURE     (0U)
/*! @brief IPWM support decoder phase z interrupt */
#define CONFIG_IPWM_SUPPORT_PHASEZ_INT      (1U)
/*! @brief IPWM support decoder direction */
#define CONFIG_IPWM_SUPPORT_DECODER_DIR     (1U)
/*! @brief IPWM instance counts */
#define CONFIG_IPWM_INSTANCE_COUNT          (2U)

/********************* SPWM module config *************************************/
/*! @brief Array initializer of SPWM peripheral register base pointers */
#define CONFIG_SPWM_REG_BASE_PTRS           { SPWM0, SPWM1, SPWM2 }
/*! @brief Array initializer of SPWM peripheral base addresses */
#define CONFIG_SPWM_BASE_ADDRS              { SPWM0_BASE, SPWM1_BASE, SPWM2_BASE }
/*! @brief Array initializer of SPWM clk name */
#define CONFIG_SPWM_CLOCK_NAMES             { CLK_SPWM0, CLK_SPWM1, CLK_SPWM2 }
/*! @brief Array initializer of SPWM module name */
#define CONFIG_SPWM_MODULE_NAMES            { MODULE_SPWM0, MODULE_SPWM1, MODULE_SPWM2 }
/*! @brief Channel interrupt vectors for the SPWM peripheral type */
#define CONFIG_SPWM_CHANNEL_IRQS            { SPWM0_Channel_IRQn, SPWM1_Channel_IRQn, SPWM2_Channel_IRQn }
/*! @brief Fault interrupt vectors for the SPWM peripheral type */
#define CONFIG_SPWM_FAULT_IRQS              { SPWM0_Fault_IRQn, SPWM1_Fault_IRQn, SPWM2_Fault_IRQn }
/*! @brief Overflow interrupt vectors for the SPWM peripheral type */
#define CONFIG_SPWM_OVERFLOW_IRQS           { SPWM0_Overflow_IRQn, SPWM1_Overflow_IRQn, SPWM2_Overflow_IRQn }
/*! @brief SPWM unified interrupt */
#define CONFIG_SPWM_UNIFIED_IRQ_FEATURE     (0U)
/*! @brief SPWM instance counts */
#define CONFIG_SPWM_INDEPENDENT_FAULT_INT   (1U)
/*! @brief SPWM instance counts */
#define CONFIG_SPWM_INSTANCE_COUNT          (3U)

/********************* ICM module config **************************************/
/*! @brief Array initializer of ICM peripheral register base pointers */
#define CONFIG_ICM_REG_BASE_PTRS            { ICM }
/*! @brief Array initializer of ICM peripheral base addresses */
#define CONFIG_ICM_BASE_ADDRS               { ICM_BASE }
/*! @brief Array initializer of ICM clk name */
#define CONFIG_ICM_CLOCK_NAMES              { CLK_ICM }
/*! @brief Array initializer of ICM module name */
#define CONFIG_ICM_MODULE_NAMES             { MODULE_ICM }
/*! @brief ICM instance counts */
#define CONFIG_ICM_INSTANCE_COUNT           (1U)
/*! @brief ICM support SPWM2 trigger */
#define CONFIG_ICM_SUPPORT_SPWM2_TRIGGER    (1U)

/********************* SPI module config **************************************/
/*! @brief Array initializer of SPI peripheral register base pointers */
#define CONFIG_SPI_REG_BASE_PTRS            { SPI0, SPI1, SPI2, SPI3 }
/*! @brief Array initializer of SPI clock names */
#define CONFIG_SPI_CLOCK_NAMES              { CLK_SPI0, CLK_SPI1, CLK_SPI2, CLK_SPI3 }
/*! @brief Array initializer of SPI module names */
#define CONFIG_SPI_MODULE_NAMES             { MODULE_SPI0, MODULE_SPI1, MODULE_SPI2, MODULE_SPI3 }
/*! @brief Array initializer of SPI interrupt request numbers */
#define CONFIG_SPI_IRQS                     { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn, SPI3_IRQn }
/*! @brief Array initializer of SPI TX dma request numbers */
#define CONFIG_SPI_TX_DMA_REQS              { DMA_REQ_SPI0_TX, DMA_REQ_SPI1_TX, DMA_REQ_SPI2_TX, DMA_REQ_SPI3_TX }
/*! @brief Array initializer of SPI RX dma request numbers */
#define CONFIG_SPI_RX_DMA_REQS              { DMA_REQ_SPI0_RX, DMA_REQ_SPI1_RX, DMA_REQ_SPI2_RX, DMA_REQ_SPI3_RX }
/*! @brief SPI support new framesize */
#define CONFIG_SPI_NEW_FRAMESIZE_FEATURE    (1U)
/*! @brief SPI instance count */
#define CONFIG_SPI_INSTANCE_COUNT           (4U)
/*! @brief SPI transmit fifo depth */
#define CONFIG_SPI_TRANSMIT_FIFO_DEPTH      (2U)
/*! @brief SPI receive fifo depth */
#define CONFIG_SPI_RECEIVE_FIFO_DEPTH       (2U)
/*! @brief SPI link node number */
#define CONFIG_SPI_DMA_MAX_LINK             (5U)
/*! @brief SPI DMA trasfer size */
#define CONFIG_SPI_DMA_MAX_SIZE             (4095 * 5U)

/********************* CMP module config **************************************/
/*! @brief Array initializer of CMP peripheral register base pointers */
#define CONFIG_CMP_REG_BASE_PTRS            { CMP0 }
/*! @brief Interrupt vectors of CMP peripheral */
#define CONFIG_CMP_IRQS                     { CMP0_IRQn }
/*! @brief Array initializer of CMP clock names */
#define CONFIG_CMP_CLOCK_NAMES              { CLK_CMP0 }
/*! @brief Array initializer of CMP module names */
#define CONFIG_CMP_MODULE_NAMES             { MODULE_CMP0 }
/*! @brief Array initializer of CMP instance counts */
#define CONFIG_CMP_INSTANCE_COUNT           (1U)

/********************* WDG module config **************************************/
/*! @brief Array initializer of WDG register base pointers */
#define CONFIG_WDG_REG_BASE_PTRS            { WDG }
/*! @brief Array initializer of WDG peripheral base addresses */
#define CONFIG_WDG_BASE_ADDRS               { WDG_BASE }
/*! @brief Array initializer of WDG instance counts */
#define CONFIG_WDG_INSTANCE_COUNT           (1U)
/*! @brief WDG unlock key */
#define CONFIG_WDG_UNLOCK_VALUE             (0x2A2B0630U)
/*! @brief WDG refresh key */
#define CONFIG_WDG_REFRESH_VALUE            (0xB0B20513U)
/*! @brief WDG support function clock of HSI */
#define CONFIG_WDG_SUPPORT_FUNC_CLK_HSI     (1U)

/********************* PMC module config **************************************/
/*!
 * @brief Wake up source
 */
typedef enum {
    WAKEUP_SOURCE_CMP0   = 0U,         /*!< wakeup source cmp0 */
    WAKEUP_SOURCE_TIMER0 = 3U,         /*!< wakeup source timer0 */
    WAKEUP_SOURCE_TIMER1 = 4U,         /*!< wakeup source timer1 */
    WAKEUP_SOURCE_TIMER2 = 5U,         /*!< wakeup source timer2 */
    WAKEUP_SOURCE_TIMER3 = 6U,         /*!< wakeup source timer3 */
    WAKEUP_SOURCE_RTC    = 8U,         /*!< wakeup source rtc */
    WAKEUP_SOURCE_LVD    = 9U,         /*!< wakeup source lvd */
    WAKEUP_SOURCE_NMI    = 10U,        /*!< wakeup source nmi */
    WAKEUP_SOURCE_GPIO   = 11U         /*!< wakeup source gpio */
} pmc_wakeup_source_t;

/*!
 * @brief pmc flag
 */
typedef enum {
    PMC_FLAG_LVD_WARINING   = 1U,      /*!< lvd warining flag */
    PMC_FLAG_WAKEUP         = 2U       /*!< wakeup form stop flag */
} pmc_flag_t;

/*! @brief Wakeup from stop flag feature*/
#define CONFIG_PMC_WAKEUP_FLAG_FEATURE                        (1U)

/*! @brief NMI interrupt and wakeup enable independent feature*/
#define CONFIG_NMI_INT_WAKEUP_ENABLE_INDEPENDENT_FEATURE      (1U)

#endif /* IM94_CONFIG_H */

/*******EOF********************************************************************/

